PXS20RM Datasheet, PDF (1252/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Reset Generation Module (MC_RGM)
Table 41-9. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions (continued)
Field
Description
BE_CORE Bidirectional Reset Enable for core reset
0 RESET_B is asserted on a core reset event if the reset is enabled
1 RESET_B is not asserted on a core reset event
BE_JTAG
Bidirectional Reset Enable for JTAG initiated reset
0 RESET_B is asserted on a JTAG initiated reset event if the reset is enabled
1 RESET_B is not asserted on a JTAG initiated reset event
41.4 Functional description
41.4.1 Reset State Machine
The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of
the device are reset based on the reset source event. This is summarized in Table 41-10.
Table 41-10. MC_RGM Reset Implications
Source
What Gets Reset
External Reset Boot Mode
Assertion¹
Capture
power-on reset
all
yes
yes
‘destructive’ resets
all except some clock/reset management
external reset
all except some clock/reset management and
debug
‘functional’ resets
all except some clock/reset management and
debug
shortened ‘functional’ resets⁴ flip-flops except some clock/reset management
yes
yes
programmable²
yes
programmable² programmable³
programmable² programmable³
NOTES:
1 _{‘external reset assertion’ means that the RESET_B pin is asserted by the MC_RGM until the end of reset PHASE3}
2 _{the assertion of the external reset is controlled via the RGM_FBRE register}
3 _{the boot mode is captured if the external reset is asserted}
4 _{the short sequence is enabled via the RGM_FESS register}
NOTE
JTAG logic has its own independent reset control and is not controlled by
the MC_RGM in any way.
The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases
are correctly processed through waiting for a minimum duration and until all processes that need to occur
during that phase have been completed before proceeding to the next phase.
The state machine used to produce the reset sequence is shown in Figure 41-11.
41-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor