PXS20RM Datasheet, PDF (127/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Core_0
Power-On Reset
LSM_DPM=0
?
Yes
No
Boot in Lock
Step Mode.
Core_0 MMU setup, other
initialization including NMI Vector,
then branch to Main().
Main() runs on Core_0, setting
up the start address for Core_1
Place Reset Vector for Core_1
in register P2BOOT.
Release Reset for Core_1
by writing DPMKEY.
Operating Modes
Core_1
Core_1 runs MMU setup, other
initialization including NMI Vector.
Core_1 changes the device
mode from DRUN to RUN0.
Both cores manage
their own NMI.
Branch to Main()
Core_1 is now operational.
Core_0 is now operational.
Figure 4-1. Simplified boot process in DPM
At power-on reset (POR), Core_0 begins operation while Core_1 remains held in reset. At this time,
Core_0 must initialize its set of peripherals, set up its environment (including the NMI routine), then
branch to main. At this point, Core_0 is essentially fully operational. Now Core_0 provides the reset vector
and writes the DPMKEY, thus releasing Core_1 from reset.
Core_1 begins its execution. The first thing that it must do is initialize its set of peripherals and set up its
environment, including its NMI routine.
Core_0 then moves the chip from DRUN mode to RUN0 mode. Each core must service its own NMI
routines. It is recommended to always use Core_0 to control the chip modes in order to avoid conflicting
or inconsistent chip mode configuruations and change requests.
4.4.2.2 Software setup
During the boot sequence, Core_0 runs from reset and executes code that sets up and enables Core_1. At
that time, the system then begins operating in DPM.
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-3