PXS20RM Datasheet, PDF (372/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

e200z4d Core Complex Overview
EREF and supplementary VLE Programming Environments Manual (VLEPEM) for more information
about the VLE extension.
The processor integrates a pair of integer execution units, a branch control unit, instruction fetch unit and
load/store unit, and a multi-ported register file capable of sustaining six read and three write operations per
clock cycle. Most integer instructions execute in a single clock cycle. Branch target prefetching is
performed by the branch unit to allow single-cycle branches in many cases.
Throughout the remainder of this document, the core is referred to as the “e200z4d” when speaking of
e200z4d-specific implementations, the “e200z4xx” when speaking of a specific variety of e200z4 core, or
“e200” when referring to the whole e200 family.
Figure 17-1 shows the block diagram for the device.
Additional Features
• OnCe/Nexus 1/Nexus
3 control logic
• Dual AHB 2.v6 buses
• SPE (SIMD)
• Embedded scalar/
vector floating-point
• Power management
• Time
base/decrementer
counter
Instruction/Control Unit
Instruction Buffer
(8/16 Instructions)
Fetch Unit
Program Counter
One-Stage
Fetch
Decode
Stage
Branch Processing Unit
+ EA Calc
8-Entry Branch
Target Buffer
Two-Instruction, In-Order Dispatch
Execution Units
32 GPRs
(64-Bit)
Execute Stage
Two stages of
instruction
executions
Executes all e200z4d instructions (including
Power ISA base, SPE, and VLE categories).
As many as two instructions can execute
simultaneously.
CR
XER
LR
CTR
Additional
SPRs
Write-Back Stage
Load/Store
Unit
+ EA Calc
Two-Instruction, In-Order Write-Back
Instruction Memory Unit
Two/Four
Instructions
Software-Managed
L1 Unified MMU
16-Entry
Fully Associative
TLB
•••
1-, 4-, 16-, 64-,
256 KB, 1-, 4-, 16-,
64-, 256 MB, 1-, 4 GB
page sizes
MAS
Registers
2- or 4-Way Set-Associative
4-Kbyte Instruction Cache
Instruction Bus Interface Unit
32
Address
64
Data
N
Control
Data Bus Interface Unit
32
64
N
Address
Data
Control
Figure 17-1. e200z4d block diagram
17.2 Features
Key features of the e200z4d are summarized as follows:
• Dual-issue, 32-bit Power ISA-compliant core
• Implementation of the VLE category for reduced code footprint
• In-order execution and retirement
17-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor