PXS20RM Datasheet, PDF (1324/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.5.2.7 Interrupt Filter Enable Register (IFER)
This register is used to enable or disable a digital filter counter on the interrupt pads to filter out glitches
on the inputs.
Address: Base + 0x0030
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFE[31:0]
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 47-9. Interrupt Filter Enable Register (IFER)
Table 47-9. IFER Field Descriptions
Field
IFE[x]
Description
Enable digital glitch filter on the interrupt pad input.
1: Filter is enabled
0: Filter is disabled
47.5.2.8 Pad Configuration Registers (PCR0–PCR132)
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics
associated with I/O pads. Each PCR controls the characteristics of a single pad. See Table 3-5 for the
mapping of PCR to pads.
Address: Base + 0x0040 (PCR0)(122 registers)
Base + 0x0042 (PCR1)
...
Base + 0x0148 (PCR132)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMC APC
W
PA
OBE IBE
ODE
SRC WPE WPS
Reset ₀
0
0
0
0
0
1
0
0
0
0
0
0
0
2
3
0
0
0
Figure 47-10. Pad Configuration Registers (PCR0)
NOTES:
1 _{The reset value of the IBE- bit of the Pad Configuration Registers PCR2, 3, 4, 21 is '1' in distinction from the}
remaining PCR registers
2 _{The reset value of the WPE- bit of the Pad Configuration Registers PCR2, 3, 4, 21 is '1' in distinction from the}
remaining PCR registers
3 _{The reset value of the WPS- bit of the Pad Configuration Registers PCR21 is '1' in distinction from the}
remaining PCR registers
NOTE
16- and 32-bit accesses are supported.
47-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor