PXS20RM Datasheet, PDF (960/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
30.6.1 MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
Offset MPU_Base + 0x000
Access: Read/Partial Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SPERR 0 0 0 0 0 1 0 0 0 HRL
NSP
NRGD 0 0 0 0 0 0 0
W w1c
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0
Figure 30-2. MPU Control/Error Status Register (MPU_CESR)
Table 30-3. MPU_CESR field descriptions
Field
SPERR
HRL
NSP
NRGD
VLD
Description
Slave Port n Error, where the slave port number matches the bit number. Each bit in this field
represents a flag maintained by the MPU for signaling the presence of a captured error contained in
the MPU_EARn and MPU_EDRn registers. The individual bit is set when the hardware detects an
error and records the faulting address and attributes. It is cleared when the corresponding bit is written
as a logical one. If another error is captured at the exact same cycle as a write of a logical one, this
flag remains set. A “find first one” instruction (or equivalent) can be used to detect the presence of a
captured error.
0 The corresponding MPU_EARn/MPU_EDRn registers do not contain a captured error.
1 The corresponding MPU_EARn/MPU_EDRn registers do contain a captured error.
Hardware Revision Level. This 4-bit read-only field specifies the MPU’s hardware and definition
revision level. It can be read by software to determine the functional definition of the module.
Number of Slave Ports. This 4-bit read-only field specifies the number of slave ports connected to the
MPU. For this device, NSP = 3.
Number of Region Descriptors. This 4-bit read-only field specifies the number of region descriptors
implemented in the MPU. The defined encodings include:
0b00 8 region descriptors
0b01 12 region descriptors
0b10 16 region descriptors (correct value for this device)
Valid. This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.
30.6.2 MPU Error Address Register, Slave Port n (MPU_EARn)
When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDRn register at the same time. This
register and the corresponding MPU_EDRn register contain the most recent access error; there are no
hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the
occurrence of each protection violation.
30-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor