PXS20RM Datasheet, PDF (1327/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.5.2.10 GPIO Pad Data Output Registers (GPDO)
These registers can be used to set or clear a single GPIO pad with a byte access.
Address: Base + 0x0600–0x0668 (27 registers)
0
1
2
3
4
5
6
7
8
R₀
0
0
0
0
0
0 PDO 0
W
[0]
Reset ₀
0
0
0
0
0
0
0
0
Access: User read/write
9
10
11
12
13
14
15
0
0
0
0
0
0 PDO
[1]
0
0
0
0
0
0
0
16
R₀
W
Reset ₀
17
18
19
20
21
22
23
24
25
26
27
28
29
0
0
0
0
0
0 PDO 0
0
0
0
0
0
[2]
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 47-12. Port GPIO Pad Data Output register 0–3 (GPDO0_3)
30
31
0 PDO
[3]
0
0
Table 47-12. GPDO0_3 field descriptions
Field
PDO[x]
Description
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
1: Logic high value is driven on the corresponding GPIO pad when the pad is configured as an
output
0: Logic low value is driven on the corresponding GPIO pad when the pad is configured as an
output
Example 47-1. Accessing GPDO ports
Check if GPIO exists in pin muxing table (Section 3.4, Pin muxing)
Write Pad Data Output Register for A[0] which is GPIO[0].
32 Bit write to address 0x0600 + 0x0000
==> register after write 0x--------_--------_--------_-------<GPIO[0]>
Write Pad Data Output Register for A[4] which is GPIO[4].
32 Bit write to address 0x0600 + 0x0004
==> register after write 0x--------_--------_--------_-------<GPIO[4]>
Write Pad Data Output Register for G[2] which is GPIO[89].
32 Bit write to address 0x0600 + 0x0016
==> register after write 0x--------_--------_-------<GPIO[89]>_--------
8 Bit write to address 0x0600 + 0x0017
Address for 32 Bit accesses = 0x0600 + [hex [ [GPIO Number / 4]** ]
** Returns the integer portion of the division
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
47-13