PXS20RM Datasheet, PDF (503/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

— FSM redundancy
— Parity check for the configuration registers
22.3 Block diagram
The top-level diagram of the FCCU is shown in Figure 22-1.
FAULT
FAULT if
Fault Collection and Control Unit (FCCU)
IPS
REG if
HNSHK
(Master)
HNSHK
(Slave)
PB
ALRT
ALRT
FSM1
F_WSM_D0_{OG SMRT}
WDOG SMRT
RCC0
RCC1
MC_RGM,
NMI
MC_RGM,
INTC
MC_RGM,
INTC
system clock
FCCU_F1 if FCCU_F0 if
FCCU_F[1] FCCU_F[0]
Figure 22-1. FCCU top-level diagram
As shown in Figure 22-1, the FCCU includes the following sub-modules:
• REG if: it includes the register file, the register interface, the IRQ interface and the parity block
(PB) for the configuration registers.
• HNSHK blocks (master and slave blocks): it includes the FSMs to support the handshake between
the REG if and the FSM unit due to the usage of 2 asynchronous clocks (system clock and IRCOSC
clock).
• Finite State Machine (FSM) units implement the main functions of the FCCU. These units also
include also the watchdog timer (WDOG), the SAFE mode request timer (SMRT), and the alarm
timer (ALRT).
• FAULT if: implements the interface for the fault conditioning and management
• FCCU_Fx units implement the output stage to manage the FCCU_F pins.
• RCCx units implement the redundancy control checker to monitor the FSM unit state and its
configuration.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
22-3