PXS20RM Datasheet, PDF (399/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
The basic operation of a channel is defined as:
1. The channel is initialized by software loading the transfer control descriptor into the eDMA’s
programming model, memory-mapped through the IPS space, and implemented as local memory.
2. The channel requests service; either explicitly by software, a peripheral request or a linkage from
another channel.
NOTE
The major loop executes one iteration per service request.
3. The contents of the transfer control descriptor for the activated channel is read from the local memory
and loaded into the eDMA engine’s internal register file.
4. The eDMA engine executes the data transfer defined by the transfer control descriptor, reading from the
source and writing to the destination. The number of iterations in the minor loop is automatically
calculated by the eDMA engine. The number of iterations within the minor loop is a function of the number
of bytes to transfer (nbytes), the source size (ssize) and the destination size (dsize). The completion of the
minor loop is equal to one iteration of the major loop.
5. At the conclusion of the minor loop’s execution, certain fields of the transfer control descriptor are
written back to the local TCD memory.
The process (steps 2-5) is repeated until the outer major loop’s iteration count is exhausted. At that time,
additional processing steps are completed, e.g., the optional assertion of an interrupt request signaling the
transfer’s completion, final adjustments to the source and destination addresses, etc.
For more details, consult Section 19.2.1, Register descriptions, and Section 19.3, Functional description.
19.2 Memory map/register definition
The eDMA’s programming model is partitioned into two sections, both mapped into the slave bus space:
the first region defines a number of registers providing control functions, while the second region
corresponds to the local transfer control descriptor memory.
Reading an unimplemented register bit or memory location will return the value of zero. Write the value
of zero to unimplemented register bits. Any access to a reserved memory location will result in a bus error.
Reserved memory locations are indicated in the memory map.
Many of the control registers have a bit width that matches the number of channels implemented in the
module. The unused bits are not implemented: reads return zeroes, and writes are ignored.
The eDMA does not include any logic which provides access control. Rather, this function is supported
using the standard access control logic provided by the PBRIDGE controller.
Table 19-1 is a 32-bit view of the eDMA’s memory map.
Table 19-1. eDMA 32-bit memory map
Address offset
0x0000
0x0004
Register
eDMA Control Register (DMACR)
eDMA Error Status (DMAES)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
19-3