PXS20RM Datasheet, PDF (831/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.6.6.2.4 Transmit Message Setup
To transmit a message over the FlexRay bus, the application writes the message data into the message
buffer data field and sets the commit bit CMT in the Message Buffer Configuration, Control, Status
Registers (FR_MBCCSRn). The physical access to the message buffer data field is described in
Section 26.6.3.1, Individual Message Buffers.
As indicated by Table 26-106, the application shall write to the message buffer data field and change the
commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, HLck,
HLckCCSa, HLckCCMa, or HLckCCMa. The application can change the state of a message buffer if it
issues the appropriate commands shown in Table 26-107. The state change is indicated through the
FR_MBCCSRn[EDS] and FR_MBCCSRn[LCKS] status bits.
If the transmit message buffer enters one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or
HLckCCMa the FR_MBCCSRn[DVAL] flag is negated.
26.6.6.2.5 Message Transmission
As a result of the message buffer search described in Section 26.6.7, Individual Message Buffer Search,
the CC triggers the message available transition MA for up to two transmit message buffers. This changes
the message buffer state from Idle to CCMa and the message buffers can be used for message transmission
in the next slot.
The CC transmits a message from a message buffer if both of the following two conditions are fulfilled at
the start of the transmission slot:
1. the message buffer is in the message available state CCMa
2. the message data are still valid, i.e. FR_MBCCSRn[CMT] = 1
In this case, the CC triggers the TX transition and changes the message buffer state to CCTx. A transmit
message buffer timing and state change diagram for message transmission is given in Figure 26-131. In
this example, the message buffer with message buffer number n is Idle at the start of the search slot,
matches the slot and cycle number of the next slot, and message buffer data are valid, i.e.
FR_MBCCSRn[CMT] = 1.
Idle
MA
MT ^start
MT ^start
search[s+1]
TX
CCMa
CCTx
message transmit
slot s
slot s+1
Figure 26-131. Message Transmission Timing
SSS SU
CCSu ^Idle
MT ^start
slot s+2
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-119