PXS20RM Datasheet, PDF (728/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.5 System Memory Base Address Register (FR_SYMBADR)
Base + 0x0004
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[31:16]
W
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-4. System Memory Base Address High Register (FR_SYMBADHR)
Base + 0x0006
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[15:4]
W
0000
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-5. System Memory Base Address Low Register (FR_SYMBADLR)
NOTE
The system memory base address must be set before the CC is enabled.
The system memory base address registers define the base address of the FlexRay memory area within the
system memory. The base address is used by the BMIF to calculate the physical memory address for
system memory accesses.
Table 26-10. FR_SYMBADR Field Descriptions
Field
SMBA
Description
System Memory Base Address — This is the value of the system memory base address for the
individual message buffers and sync frame table. This is the value of the system memory base address
for the receive FIFO if the FIFO address mode bit FR_MCR[FAM] is set to 1. It is defines as a byte address.
26.5.2.6 Strobe Signal Control Register (FR_STBSCR)
Base + 0x0008
16-bit write access required
Write: Anytime
0
1
R0 0
W WMD
Rese
t
0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
00
000
00
SEL
ENB
STBPSEL
00000000000000
Figure 26-6. Strobe Signal Control Register (FR_STBSCR)
This register is used to assign the individual protocol timing related strobe signals given in Table 26-12 to
the external strobe ports. Each strobe signal can be assigned to at most one strobe port. Each write access
26-16
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor