PXS20RM Datasheet, PDF (800/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.75 ECC Error Injection Address Register (FR_EEIAR)
Base + 0x00FA
Write: IDL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MID
W
BANK
ADDR
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-106. ECC Error Injection Address Register (FR_EEIAR)
This register defines the memory module, bank, and address where the ECC error has to be injected.
Table 26-86. FR_EEIAR Field Descriptions
Field
MID
BANK
ADDR
Description
Memory Identifier — This flag defines the memory instance for ECC error injection.
0 PE DRAM
1 CHI LRAM
Memory Bank — This field defines the memory bank for ECC error injection.
For MID=0:
000 BANK0: PE DRAM [7:0]
001 BANK1: PE DRAM [15:8]
others reserved
For MID=1:
000 BANK0: FR_MBCCFR(2n)
001 BANK1: FR_MBFIDR(2n)
010 BANK2: FR_MBIDXR(2n)
011 BANK3: FR_MBCCFR(2n+1)
100 BANK4: FR_MBFIDR(2n+1)
101 BANK5: FR_MBIDXR(2n+1)
others reserved
Memory Address — This flag defines the memory address for ECC error injection.
26.5.2.76 ECC Error Injection Data Register (FR_EEIDR)
Base + 0x00FC
Write: IDL
0
R
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA
000000000000000
Figure 26-107. ECC Error Injection Data Register (FR_EEIDR)
This register defines the data distortion pattern for the error injection write. The number of valid bits
depends on the selected memory and memory bank as shown in Table 26-84.
26-88
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor