PXS20RM Datasheet, PDF (1105/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not
affect the clock gating behavior until a new mode transition request is generated.
Whenever the processor enters a debug session during any mode, the following occurs for each peripheral:
• The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise,
the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further
modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers
during a debug session will take affect immediately without requiring any new mode request.
32.4.7 Application example
Figure 32-27 shows an example application flow for requesting a mode change and then waiting until the
mode transition has completed.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
32-49