PXS20RM Datasheet, PDF (527/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
Offset: 0x0E4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-23. FCCU IRQ Enable Register (FCCU_IRQ_EN)
Table 22-22. FCCU_IRQ_EN field descriptions
Field
Description
CFG_TO_IEN Configuration Time-out Interrupt Enable
0: Configuration time-out interrupt disabled
1: Configuration time-out interrupt enabled
This bit can be read and written by the software.
22.6.21 FCCU XTMR Register (FCCU_XTMR)
The FCCU_XTMR register contains the read values of the Alarm, Watchdog or Safe Mode Request Timer.
These timers are clocked on the IRCOSC clock.
The SW application executes the timer read operation by the following sequence:
• to set the OP17 or OP18 or OP19 operation into the FCCU_CTRL.OPR field
• to wait for the completion of the operation (FCCU_CTRL.OPS field)
• to read the FCCU_XTMR register
Table 22-23. Timer state/value
TIMER
ALARM
SMRT
CFG
CONFIG state
00000000h
00000001h
Running
NORMAL state
Initial value
Initial value
0001FFFFh
ALARM state
Running
—
0001FFFFh
FAULT state
Idle/End of count
Running/End of count
0001FFFFh
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
22-27