PXS20RM Datasheet, PDF (1186/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Register Protection (REG_PROT)
40.3.2 Register descriptions
This section describes in address order all the REG_PROT registers. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order.
Figure 40-3. Key to register fields
Always 1 Always 0 R/W BIT Read- BIT Write-
Write 1 BIT Self-clear 0 N/A
reads 1
reads 0
bit
only bit
only bit _BIT to clear _w1c
bit _BIT
40.3.2.1 Module registers (MR0-6143)
This is the lower 6 KB module memory space which holds all the functional registers of the module that
is protected by the REG_PROT module.
40.3.2.2 Module register and set soft lock bit (LMR0-6143)
This is memory area #3 that provides mirrored access to the MR0-6143 registers with the side effect of
setting Soft Lock Bits in case of a write access to a MR that is defined as protectable by the locking
mechanism. Each MR is protectable by one associated bit in a SLBRn[SLBm], according to the mapping
described in Table 40-2.
40.3.2.3 Soft lock bit register (SLBR0-1535)
These registers hold the soft lock bits for the protected registers in memory area #1.
Offset: 0x3800-0x3DFF
R
W
Reset
0
0
WE0
0
1
0
WE1
2
0
WE2
3
0
WE3
4
SLB0
5
SLB1
0
0
0
0
0
Figure 40-4. Soft lock bit register (SLBRn)
Access: Read always
Supervisor write
6
7
SLB2
SLB3
0
0
40-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor