PXS20RM Datasheet, PDF (589/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
desirable to only enable prefetches for the processor core to limit the number of buffers used for other
masters.
The PFLASH2P occupies a 512 MByte region of the address space. The actual flash array is
multiply-mapped within this space. Upper address lines haddr[28:24] are used to provide additional
control which allows the PFLASH2P responses on the AHB to be varied in order to provide for timing
emulation of alternate memory types. See Section 23.2.3.6, Wait-state emulation for additional
information. The PFLASH2P memory map is shown in Figure 23-24. Recall the PFLASH2P supports a
16 MByte (24 address bits) physical flash array size.
0bYYYZZ_0000_0000_0000_0000_0000_0000 -
0bYYYZZ_1111_1111_1111_1111_1111_1111
Flash Array
Access
YYYZZ - additional primary (YYY) and secondary (ZZ) wait-states for emulation
Figure 23-24. PFLASH2P Memory Map
Write accesses must be either word or doubleword in size, and must be aligned. Unaligned writes and byte
or halfword writes result in an error termination on the AHB side, and no flash array write is initiated.
Write addresses are captured from the AHB, and a write to the flash is initiated once data from the AHB
is available on the following cycle. Write data is held valid until the flash write cycle completes.
23.2.2 Registers
CAUTION
Software executing from flash memory must not write to registers that
control flash behavior (such as wait state settings or prefetch
enable/disable). Doing so can cause data corruption.
NOTE
Flash memory configuration registers should be written only with 32-bit
write operations to avoid any issues associated with register incoherency
caused by bit fields spanning smaller size (8-, 16-bit) boundaries.
Within the module’s programming model, there are a variety of control and configuration fields. Some are
associated with the operating configuration of the flash memory array, while others are related to the
behavior of the AHB master ports.
The PFLASH controller does not provide completely symmetric capabilities for the flash memory array.
First, consider the operating configuration of the flash memory array. In particular, there are 4 unique
configuration fields that are associated with the array. These include all the parameters associated with the
timing (read and write wait states, address pipeline control) as well as the read-while-write control field.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-39