PXS20RM Datasheet, PDF (414/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the DMAINTL
register.
See Figure 19-14 and Table 19-22 for the DMAINTL definition.
Register address: DMA_Offset + 0x0024
0123456789
R
0000000000
W
RESET: 0 0 0 0 0 0 0 0 0 0
10 11 12 13 14 15
000000
000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R INT1 INT1 INT1 INT1 INT1 INT1 INT9 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
W
543210
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented
Figure 19-14. eDMA Interrupt Request Low (DMAINTL) Register
Name
INTn,
n = 0,... 15
Table 19-22. DMAINTL field descriptions
Description
DMA Interrupt Request n
Value
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
19.2.1.14 eDMA Error Low (DMAERRL) Register
The DMAERRL register provides a bit map for the implemented channels signaling the presence of an
error for each channel. The eDMA engine signals the occurrence of a error condition by setting the
appropriate bit in this register. The outputs of this register are enabled by the contents of the DMAEEIL
register, then logically summed to form an error interrupt request which is then routed to the platform’s
interrupt controller. During the execution of the interrupt service routine associated with any eDMA errors,
it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a
write to the DMACERR register in the interrupt service routine is used for this purpose. Recall the normal
eDMA channel completion indicators, setting the transfer control descriptor done flag and the possible
assertion of an interrupt request, are not affected when an error is detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the DMAEEIL register. The state of any given channel’s error indicators is
affected by writes to this register; it is also affected by writes to the DMACERR register. On writes to the
DMAERRL, a one in any bit position clears the corresponding channel’s error status. A zero in any bit
position has no affect on the corresponding channel’s current error status. The DMACERR register is
provided so the error indicator for a single channel can easily be cleared.
See Figure 19-15 and Table 19-23 for the DMAERRL definition.
19-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor