PXS20RM Datasheet, PDF (483/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Register address: ECSM Base + 0x0043
0
R
0
W
RESET:
0
1
2
3
4
0
0
EPR1BR
EPF1BR
0
0
0
0
5
6
7
0
EPRNCR
EPFNCR
0
0
0
= Unimplemented
Figure 21-8. ECC Configuration (ECR) Register
Table 21-10. ECR field descriptions
Field
Description
EPR1BR Enable Platform RAM 1-bit Reporting
0 = Reporting of single-bit platform RAM corrections is disabled.
1 = Reporting of single-bit platform RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit platform RAM correction generates a non-critical fault as signalled by the assertion of
ESR[R1BC]. The address, attributes and data are also captured in the PREAR, PRESR, PREMR,
PREAT, PREDRL, and PREDRH registers.
EPF1BR Enable Platform Flash Memory 1-bit Reporting
0 = Reporting of single-bit platform flash memory corrections is disabled.
1 = Reporting of single-bit platform flash memory corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit platform flash memory correction generates a non-critical fault as signalled by the assertion of
ESR[F1BC]. The address, attributes and data are also captured in the PFEAR, PFEMR, PFEAT,
PFEDRL, and PFEDRH registers.
EPRNCR Enable Platform RAM Non-Correctable Reporting
0 = Reporting of non-correctable platform RAM errors is disabled.
1 = Reporting of non-correctable platform RAM errors is enabled.
The occurrence of a non-correctable multi-bit platform RAM error generates a critical fault as signalled
by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in the
PREAR, PRESR, PREMR, PREAT, PREDRL, and PREDRH registers.
EPFNCR Enable Platform Flash Memory Non-Correctable Reporting
0 = Reporting of non-correctable platform flash memory errors is disabled.
1 = Reporting of non-correctable platform flash memory errors is enabled.
The occurrence of a non-correctable multi-bit platform flash memory error generates a critical fault as
signalled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in
the PFEAR, PFEMR, PFEAT, PFEDRL, and PFEDRH registers.
21.4.2.10 ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last, properly-enabled memory event to be detected. ECC
interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection
and the combination of the two as defined by the following boolean equations:
ECSM_ECC1BIT_IRQ
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-9