PXS20RM Datasheet, PDF (563/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Table 23-1. C90FL flash memory map (continued)
FLASH_BASE address offset
Use
Block
0x00F0_0000
Flash memory shadow block, for general use
S
0x00F0_3DD8
System censoring passcode
0x00F0_3DE0
System censoring
0x00F0_3DE8
LML default
0x00F0_3DF0
HBL default
0x00F0_3DF8
SLL default
0x00F0_3E00
PFAPR
0x00F0_3E08
BIU3 default
0x00F0_3E10
BIU4 default
0x00F0_4000 – 0x00FF_FFFF Reserved
0x0100_0000 – 0x1FFF_FFFF Flash memory emulation mapping
—
NOTES:
1_{For Read while Write operations, shadow block behaves as if it is in all partitions.}
Size
(KB)
16
496
Partition
All¹
—
Table 23-2. Register memory map
Address
Use
FLASH_REGS_BASE + 0x0
FLASH_REGS_BASE + 0x4
FLASH_REGS_BASE + 0x8
FLASH_REGS_BASE + 0xC
FLASH_REGS_BASE + 0x10
FLASH_REGS_BASE + 0x14
FLASH_REGS_BASE + 0x18
MCR
LML Register (LML)
HBL Register (HBL)
SLL Register (SLL)
LMS Register (LMS)
HBS Register (HBS)
ADR Register (ADR)
FLASH_REGS_BASE + 0x1C
FLASH_REGS_BASE + 0x24
FLASH_REGS_BASE + 0x2C
FLASH_REGS_BASE + 0x3C
FLASH_REGS_BASE + 0x40
FLASH_REGS_BASE + 0x44
FLASH_REGS_BASE + 0x48
FLASH_REGS_BASE + 0x4C
FLASH_REGS_BASE + 0x50
PFlash Configuration Register 0 (PFCR0)
PFlash Access Protection Register (PFAPR)
BIU4
UT0
UT1
UT2
UM0
UM1
UM2
FLASH_REGS_BASE + 0x54
UM3
FLASH_REGS_BASE + 0x58
UM4
FLASH_SHADOW_BASE + 0x3DD8 NVPWD0
FLASH_SHADOW_BASE + 0x3DDC NVPWD1
FLASH_SHADOW_BASE + 0x3DE0 NVSCI
Location
on page 23-13
on page 23-18
on page 23-20
on page 23-21
on page 23-22
on page 23-23
on page 23-24
on page 23-40
on page 23-44
on page 23-25
on page 23-25
on page 23-27
on page 23-27
on page 23-28
on page 23-28
on page 23-28
on page 23-28
on page 23-28
on page 23-31
on page 23-32
on page 23-32
23.1.6.1 Module Configuration Register (MCR)
The MCR register is defined in Figure 23-3 and Table 23-3.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-13