PXS20RM Datasheet, PDF (235/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
11.4.2.1 Auxiliary clock dividers
The MC_CGM generates the following derived clocks:
• motor control clock - controlled by the CGM_AC0_DC0 register
• sine wave generator clock - controlled by the CGM_AC0_DC1 register
• FlexRay clock - controlled by the CGM_AC1_DC0 register
• FlexCAN clock - controlled by the CGM_AC2_DC0 register
11.4.3 Functional description of dividers
Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the
following control registers for built-in dividers:
• Section 11.3.1.4, System Clock Divider Configuration Registers (CGM_SC_DC0)
• Section 11.3.1.6, Auxiliary Clock 0 Divider Configuration Registers (CGM_AC0_DC0…1)
• Section 11.3.1.8, Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
• Section 11.3.1.10, Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set
to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.
11.4.4 Output clock multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as
output clock sources. The selection is done via the CGM_OCDS_SC register.
11.4.5 Output Clock Division Selection
16 MHz int. RC osc.
0
4-40 MHz crystal osc.
1
system FMPLL
2
secondary (80 MHz) FMPLL
3
CGM_OC_EN Register
3
2 ^{’0’}
1
0
Port pin B[6]
CGM_OCDS_SC.SELCTL
Register
CGM_OCDS_SC.SELDIV
Register
Figure 11-21. MC_CGM Output Clock Multiplexer and Port Pin B[6] Generation
The MC_CGM provides the following output signals for the output clock generation:
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
11-21