PXS20RM Datasheet, PDF (206/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
For algorithm S, the three steps must be atomic. In CTU mode, this is managed by CTU itself i.e. CTU has
to send three triggers (one for each step) asserting ctu_adc_st_en and updating ctu_adc_st_step for each
step.
Channel Cnversion Command Registers (CLRx) in CTU allow to setup a self test command, choosing also
among the algorithms available. See Table 9-46 and Table 9-47.
Table 9-46. CTU-CLRx-ST1, ST0 meaning
ST1 bit
0
0
1
1
ST0 bit
0
1
0
1
Command meaning
No self test
Single conversion
Self test command
No self test command
Dual conversion
No self test
Dual conversion
ALG1
0
0
1
1
Table 9-47. CTU-CLRx-ALG1, ALG0 meaning
ALG0
Algorithm meaning
0
Algorithm S
1
Algorithm RC
1
Algorithm C
1
Algorithm FULL
The algorithm S must be executed as an atomic test without interleaved user conversions.
Step 0:
• VBGAP/VREF test
• Step1: VDD/VREF test
• Step2: VREF/VREF test
CTU sends three triggers (one for each step) asserting ctu_adc_st_en and updating ctu_adc_st_step for
each step.
The RC and C algorithm can be executed, programming the CLRx registers, in one of the following
schemes:
• Burst mode: when the CTU schedules the execution of the CLRx register configured for the self
testing, both the algorithms RC and C are executed in burst mode (step0-algRC, step1-algRC,
...stepN-algRC, step0-algC, step1-algC, ... stepM-algC).
• Interleaved mode: when the CTU schedules the execution of the CLRx register configured for the
self testing, a single step of the algorithm RC or C is executed according to an internal counter. In
this mode the ADC self testing procedure is distributed and the functional conversions are not
stalled for a long time.
9-48
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor