PXS20RM Datasheet, PDF (330/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-3. DSPI_MCR field descriptions (continued)
Field
Description
DIS_RXF
Disable Receive FIFO. When DIS_RXF is set, the RX FIFO acts as a single-entry (unit depth) FIFO.
Therefore, serial operation is performed as if the FIFO has only one valid entry space for serial-word
transfer. See Section 16.4.2.3, FIFO Disable Operation, for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
CLR_TXF
Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO
Counter. The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO Counter
1 Clear the TX FIFO Counter
CLR_RXF
Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX
Counter. The CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO Counter
1 Clear the RX FIFO Counter
SMPL_PT
Sample Point. SMPL_PT field controls when the DSPI master samples SIN in Modified Transfer
Format. Figure 16-25 shows where the master can sample the SIN pin.
00 DSPI samples SIN at driving SCK edge.
01 DSPI samples SIN one system clock after driving SCK edge
10 DSPI samples SIN two system clocks after driving SCK edge
11 Reserved
PES
(on cut2/3
only)
HALT
Parity Error Stop. This bit controls SPI operation when a parity error detected in received SPI frame.
0 SPI frames transmission continue.
1 SPI frames transmission stop.
Halt. The HALT bit starts and stops DSPI transfers. See Section 16.4.1, Start and Stop of DSPI
Transfers, for details on the operation of this bit.
0 Start transfers
1 Stop transfers
16.3.2.2 DSPI Hardware Configuration Register (DSPI_HCR) [cut2/3 only]
The DSPI_HCR provides particular implementation details about the DSPI module, i.e. number of
Receive and Transmit FIFO entries, and the number of CTAR registers. It is a read-only register.
Address: DSPI_BASE + 0x4
0
1
2
3
R 0 PISR 0 0
W
Reset —¹ — 0 0
Access:
4
5
6
7
8
9
10 11 12 13 14 15
0
CTAR
TXFR
RXFR
0 ———————————
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-5. DSPI Hardware Configuration Register (DSPI_HCR) [cut2/3 only]
16-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor