PXS20RM Datasheet, PDF (314/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
gives up the slave port by either running and IDLE cycle to the slave port or running a valid access to a
location other than the slave port.
If the current master loses control of the slave port because a higher priority master takes it away, the slave
port will not incur any wasted cycles. The current master has its current cycle terminated by the slave port
at the same time the new master’s address and control information are recognized by the slave port. This
appears as a seamless transition on the slave port.
If the current master is being wait-stated when the higher priority master makes its request, then the current
master will be allowed to make one more transaction on the slave bus before giving it up to the new master.
Figure 15-5 illustrates the effect of a higher priority master taking control of the bus when the slave port
is programmed for a fixed priority mode of operation.
1
2
3
4
5
6
7
hclk
m2 request
m3 request
m4 request
m5 request
Highest
Priority
Requester
Address/Cntrl
owner
htrans
Master 5 Master 5 Master 4 Master 3 Master 2
XBAR Master 5
Master 5
IDLE
NSEQ
NSEQ
Master 3
Master 2
NSEQ
hready
8
9
10
Master 4
None
Master 3 Master 4 XBAR
NSEQ NSEQ IDLE
Figure 15-5. Low to high priority mastership change
If the current master is the highest priority master and it gives up the slave port by running an IDLE cycle
or by running a valid cycle to another location other than the slave port the next highest priority master
will gain control of the slave port. If the current access incurs any wait states then the transition will be
seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait
states then one IDLE cycle will be forced onto the slave bus by the XBAR before the new master will be
able to take control of the slave port. If no other master is requesting the bus then IDLE cycles will be run
by the XBAR but no bandwidth will truly be lost since no master is making a request. Figure 15-6
illustrates the effect of a higher priority master giving up control of the bus.
15-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor