PXS20RM Datasheet, PDF (581/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Table 23-17. UM3 Field Descriptions
Field
Description
0-31
See the description of the MISR in Table 23-14.
MISR[127:96]
Flash Memory
23.1.6.12.5 UM4 Register
The following field and bit descriptions fully define the UM4 register.
Offset 0x0058
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R_{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
W
MISR
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 23-17. UM4 register
MISR register functions are shown in Table 23-18.
Table 23-18. UM4 field descriptions
Field
MISR[144:128]
Description
See the description of the MISR in Table 23-14.
23.1.6.13 Nonvolatile Private Censorship Password 0 register (NVPWD0)
Offset 0x3DD8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PWD[31:16]
W
Reset 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PWD[15:0]
W
Reset 1 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0
Figure 23-18. Nonvolatile Private Censorship Password 0 register (NVPWD0)
The Nonvolatile Private Censorship Password 0 register (NVPWD0) contains the 32 LSB of the password
used to validate the censorship information contained in the NVSCI register.
Table 23-19. NVPWD0 field descriptions
Field
PWD
Description
These bits represent the private censorship password.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-31