PXS20RM Datasheet, PDF (957/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
30.3 Features
The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar
slave AHB ports to continuously monitor the legality of every memory reference generated by each bus
master in the system. The feature set includes:
• Support for 16 memory region descriptors
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— 4 bus masters that support the traditional {read, write, execute} permissions with independent
definitions for supervisor and user mode accesses.
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter only the access rights of a descriptor
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software. See Section 30.7.2,
Putting it all together and AHB error terminations, for details and Section 30.9, Application
information, for an example.
• Support for 3 AHB slave port connections
— MPU hardware continuously monitors every AHB slave port access using the pre-programmed
memory region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit. In the event of an
access error, the AHB reference is terminated with an error response and the MPU inhibits the
bus cycle being sent to the targeted slave device. This results in a Machine Check Exception.
— 64-bit error registers, one for each AHB slave port, capture the last faulting address, attributes
and “detail” information
• Global MPU enable/disable control bit provides a mechanism to easily load region descriptors
during system startup or allow complete access rights during debug with the module disabled
On this device, the two instantiations of the MPU are referred to as MPU_0 (attached to the slave side of
XBAR_0) and MPU_1 (attached to the slave side of XBAR_1). Both instantiations are identical and do
not differ in LS Mode or DP Mode.
The MPU port allocation is shown in Table 30-1.
Table 30-1. MPU port allocation
AXBS slave port
Flash memory
SRAM
Peripheral bridge
Port 0
Port 1
Port 2
MPU_0
Port 0
Port 1
Port 2
MPU_1
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
30-3