PXS20RM Datasheet, PDF (1322/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
Address: Base + 0x0014
Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIF[31:0]
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 47-5. Interrupt Status Flag Register (ISR)
Table 47-5. ISR Field Descriptions
Field
EIF[x]
Description
External Interrupt Status Flag x
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
0: No interrupt event has occurred on the pad
1: An interrupt event as defined by IREER[x] and IFEER[x] has occurred
47.5.2.4 Interrupt Request Enable Register (IRER)
This register is used to enable the interrupt messaging to the interrupt controller.
Address: Base + 0x0018
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIRE[31:0]
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 47-6. Interrupt Request Enable Register (IRER)
Table 47-6. IRER Field Descriptions
Field
EIRE[x]
Description
External Interrupt Request Enable x
1: A set EIR[x] bit causes an interrupt request
0: Interrupt requests from the corresponding EIR[x] bit are disabled
47-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor