PXS20RM Datasheet, PDF (762/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.38 Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)
Base + 0x004A
Write: POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0
W
FMSK
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-38. Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)
This register defines the sync frame acceptance filter mask. For details on filtering see Section 26.6.15.1,
Sync Frame Acceptance Filtering.
Table 26-43. FR_SFIDAFMR Field Descriptions
Field
FMSK
Description
Filter Mask — This field defines the mask for the sync frame acceptance filtering.
26.5.2.39 Network Management Vector Registers (FR_NMVR0–FR_NMVR5)
Base + 0x004C (FR_NMVR0)
Base + 0x004E (FR_NMVR1)
Base + 0x0050 (FR_NMVR2)
Base + 0x0052 (FR_NMVR3)
Base + 0x0054 (FR_NMVR4)
Base + 0x0056 (FR_NMVR5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
NMVP[15:8]
NMVP[7:0]
W
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-39. Network Management Vector Registers (FR_NMVR0–FR_NMVR5)
Each of these six registers holds one part of the Network Management Vector. The length of the Network
Management Vector is configured in the Network Management Vector Length Register (FR_NMVLR). If
FR_NMVLR is programmed with a value that is less than 12 bytes, the remaining bytes of the Network
Management Vector Registers (FR_NMVR0–FR_NMVR5), which are not used for the Network
Management Vector accumulating, will remain 0.
The NMVR provides accrued information over all received NMVs in the last communication cycle. All
NMVs received in one cycle are ORed into the NMVR. The NMVR is updated at the end of the
communication cycle.
26-50
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor