PXS20RM Datasheet, PDF (1335/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Int
Vectors
System Integration Unit Lite (SIUL)
IRQ_31_24
IRQ_23_16
IRQ_15_08
IRQ_07_00
OR
OR
OR
OR
Interrupt enable
IRE[31:0]
Glitch filter Prescaler
IFCP[3:0]
Glitch filter Counter_n
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[31:0]
EIF[31:24]
EIF[23:16]
EIF[15:8]
Edge Detection
Glitch Filter
EIF[7:0]
Pads
Figure 47-20. External Interrupt pad diagram
Interrupt Edge Enable
Rising
IREE[31:0]
Falling
IFEE[31:0]
47.6.4.1 External interrupt management
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt
Request Enable Register (IRER - Section 47.5.2.4, Interrupt Request Enable Register (IRER)). A pad
defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an
active falling edge or both edges being active. A setting of having both edge events disabled is reserved
and should not be configured.
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag which is held in the Flag register (ISR -
Section 47.5.2.3, Interrupt Status Flag Register (ISR)). This register is a write-1-to-clear register type,
preventing inadvertent overwriting of other flags in the same register.
47.7 Pin muxing
For pin muxing, see Chapter 3, Signal Description.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
47-21