PXS20RM Datasheet, PDF (997/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-7. BDRM access in UART mode (continued)
Access
Mode¹
Word length²
IPS operation result
Read Half-word2
Read Half-word3
FIFO
FIFO
Half-word
Half-word
OK
IPS transfer error
Read Word
Write Byte4-5-6-7
Write Half-word2-3
Write Word
Read Byte4-5-6-7
FIFO
FIFO
FIFO
FIFO
BUFFER
Half-word
Byte/Half-word
Byte/Half-word
Byte/Half-word
Byte/Half-word
IPS transfer error
IPS transfer error
IPS transfer error
IPS transfer error
OK
Read Half-word2-3
Read Word
Write Byte4-5-6-7
Write Half-word2-3
BUFFER
BUFFER
BUFFER
BUFFER
Byte/Half-word
Byte/Half-word
Byte/Half-word
Byte/Half-word
OK
OK
IPS transfer error
IPS transfer error
Write Word
BUFFER
Byte/Half-word
NOTES:
1 _{As specified by UARTCR[RFBM]}
2 _{As specified by the WL1 and WL0 bits of the UARTCR register}
IPS transfer error
Table 31-8 lists some common scenarios, controller responses, and suggestions when the LINFlexD
controller is acting as a UART receiver.
Table 31-8. UART receiver scenarios
Scenario
Responses and suggestions
The software does not know (in advance) how many bytes Do not program UARTCR[RDFLRFC] in advance. When
will be received.
this field is zero (as it is after reset), reception occurs on a
byte-by-byte basis. Therefore, the state machine will
move to IDLE state after each byte is received.
UARTCR[RDFLRFC] is programmed for a certain number The reception will hang. In this case, the software must
of bytes received, but the actual number of bytes received monitor the UARTSR[TO] field, and move to IDLE state by
is smaller.
setting LINCR1[SLEEP].
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-21