PXS20RM Datasheet, PDF (186/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
Field
WDG_EOA_S
ERR_C
ERR_RC
ERR_S2
ERR_S1
ERR_S0
STEP_C
STEP_RC
Table 9-31. STSR1 field descriptions (continued)
Description
This bit indicates that Algorithm S has been completed. This bit is set after the last step of
algorithm S is executed. It generates an interrupt if enabled (STCR2[MSKWDG_EOA_S] = 1).
This bit is set only if STAW0R[WDTE] = 1.
For CTU conversions, this bit is significant only for Burst mode of operation.
Indicates an error on the self testing channel (algorithm C). It generates an interrupt if enabled
(STCR2[MSKERR_C] = 1). It provides the fault indication to the FCCU, asserting the
programmed fault line (STCR2[FMAn])
You can also set the ERR_C bit (fault injection) by setting the STCR2[SERR] bit. In this case
the CF or NCF lines are asserted according to the STCR2[FMAn] mapping.
0 No C-algorithm error has occurred
1 A C-algorithm error has occurred
Indicates an error on the self testing channel (algorithm RC). It generates an interrupt if
enabled (STCR2[MSKERR_RC] = 1). It provides the fault indication to the FCCU, asserting
the programmed fault line (STCR2[FMAn])
You can also set the ERR_RC bit (fault injection) by setting the STCR2[SERR] bit. In this case
the CF or NCF lines are asserted according to the STCR2[FMAn] mapping.
0 No RC-algorithm error has occurred
1 An RC-algorithm error has occurred
Indicates an error on the self testing channel (algorithm SUPPLY, step 2). It generates an
interrupt if enabled (STCR2[MSKERR_S2] = 1). It provides the fault indication to the FCCU,
asserting the programmed fault line (STCR2[FMAn])
You can also set the ERR_S2 bit (fault injection) by setting the STCR2[SERR] bit. In this case
the CF or NCF lines are asserted according to the STCR2[FMAn] mapping.
0 No error has occurred on the sampled signal
1 An error has occurred on the sampled signal
Indicates an error on the self testing channel (algorithm SUPPLY, step 1). It generates an
interrupt if enabled (STCR2[MSKERR_S1] = 1). It provides the fault indication to the FCCU,
asserting the programmed fault line (STCR2[FMAn])
You can also set the ERR_S1 bit (fault injection) by setting the STCR2[SERR] bit. In this case
the CF or NCF lines are asserted according to the STCR2[FMAn] mapping.
0 No VDD error has occurred
1 A VDD error has occurred
Indicates an error on the self testing channel (algorithm SUPPLY, step 0). It generates an
interrupt if enabled (STCR2[MSKERR_S0] = 1). It provides the fault indication to the FCCU,
asserting the programmed fault line (STCR2[FMAn])
You can also set the ERR_S0 bit (fault injection) by setting the STCR2[SERR] bit. In this case
the CF or NCF lines are asserted according to the STCR2[FMAn] mapping.
0 No VREF error has occurred
1 A VREF error has occurred
Step of the algorithm C when an ERR_C has occurred.
0.. (NUM_C_STEPS-1) => algorithm C
Step of the algorithm RC when an ERR_RC has occurred.
0.. (NUM_RC_STEPS-1) => algorithm RC
9-28
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor