PXS20RM Datasheet, PDF (1326/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.5.2.9 Pad Selection for Multiplexed Inputs (PSMI0_3–PSMI40_43¹)
These registers define pads as input to peripheral functions.
Figure 47-11 and Table 47-11 present the structure of the PSMI0_3 register. The structure of the other 10
PSMI registers is similar, with numbers modified appropriately.
Address: Base + 0x0500 - 0x0528 (11 registers)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
0
0
W
PADSEL0
0
0
0
0
PADSEL1
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
W
PADSEL2
0
0
0
0
PADSEL3
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 47-11. Pad Selection for Multiplexed Inputs Register (PSMI0_3)
Table 47-11. PSMI0_3 field descriptions
Field
Description
PADSEL0–3
Pad Selection Bits
Each PADSEL field selects the pad currently used for a certain input function (see Table 3-5).
Example: In Function: LIN0 RXD
PSMI32_35 PADSEL0:
00: B[3]
01: B[7]
1.PSMI43 does not exist; the register name includes the number 43 due to the sequential naming convention of these
registers.
47-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor