PXS20RM Datasheet, PDF (291/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Cyclic Redundancy Checker (CRC) Unit
X³² + X²⁶ + X²³ + X²² + X¹⁶ + X¹² + X¹¹ + X¹⁰ + X⁸ + X⁷ + X⁵ + X⁴ + X² + X + 1
CRC-32 (ethernet protocol)
Eqn. 14-3
15
12
+
11
5
+
4
Serial
data
input
(LSB
first)
0
+
Figure 14-7. CRC-CCITT engine concept scheme
The initial seed value of the CRC can be programmed initializing the CRC_CSTAT register. The concept
scheme (serial data loading) of the CRC engine is given in Figure 14-7 for the CRC-CCITT. The design
implementation executes the CRC computation in a single clock cycle (parallel data loading). A pipeline
scheme has been adopted to de-couple the IPS bus interface from the CRC engine in order to allow the
computation of the CRC at speed (zero wait states).
In case of usage of the CRC signature for encapsulation in the data frame of a communication protocol
(e.g. SPI, ..) a bit swap (MSB  LSB, LSB  MSB) and/or bit inversion of the final CRC signature can
be applied (CRC_OUTP register) before to transmit the CRC.
The usage of the CRC module is summarized in the flowchart given in Figure 14-8.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
14-7