PXS20RM Datasheet, PDF (929/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
a priority, etc. With this approach, a range of ISR request rates of 2¹⁶ could be covered, regardless of the
number of ISRs.
Reducing the number of priorities does cause some priority inversion which reduces the processor’s ability
to meet its deadlines. However, reducing the number of priorities can reduce the size and latency through
the interrupt controller. It also allows easier management of ISRs with similar deadlines that share a
resource. They can be placed at the same priority without any further priority inversion, and they do not
need to use the PCP to access the shared resource.
28.6.8 Software settable Interrupt Requests
The software settable interrupt requests can be used in two ways. They can be used to schedule a lower
priority portion of an ISR and for processors to interrupt other processors in a multiple processor system.
28.6.8.1 Scheduling a Lower Priority Portion of an ISR
A portion of an ISR needs to be executed at the PRIx value in Section 28.4.8, INTC Priority Select
Registers (INTC_PSR0_3 - INTC_PSR252_255),, which becomes the PRI value in either Section 28.4.4,
INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0), with the interrupt acknowledge. The
ISR, however, can have a portion of it which does not need to be executed at this higher priority. Therefore,
executing this later portion which does not need to be executed at this higher priority can block the
execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a
higher priority than what the later portion of the ISR needs. This priority inversion reduces the processor’s
ability to meet its deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule through the
RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount
of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher
priority portion, to set a SETx bit in Section 28.4.7, INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3 - INTC_SSCIR4_7). Writing a ‘1’ to SETx causes a software settable interrupt request.
This software settable interrupt request, which usually will have a lower PRIx value in the INTC_PSRx_x,
therefore will not cause priority inversion.
28.6.8.2 Scheduling an ISR on Another Processor
Since the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple processor
systems can schedule ISRs on the other processors. One application is that one processor simply wants to
command another processor to perform a piece of work, and the initiating processor does not need to use
the results of that work. If the initiating processor is concerned that processor executing the software
settable ISR has not completed the work before asking it to again execute that ISR, it can check if the
corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a ‘1’ to the SETx bit.
Another application is the sharing of a block of data. For example, a first processor has completed
accessing a block of data and wants a second processor to then access it. Furthermore, after the second
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. The procedure is that the first processor writes a ‘1’
to a SETx bit on the second processor. The second processor, after accessing the block of data, clears the
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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