PXS20RM Datasheet, PDF (627/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
24.3.4.10 Interrupt Flags 1 Register (IFLAG1)
This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It contains one
interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG1 bit.
If the corresponding IMASK1 bit is set, an interrupt will be generated. The Interrupt flag must be cleared
by writing it to ‘1’. Writing ‘0’ has no effect.
When the AEN bit in the MCR is set (Abort enabled), while the IFLAG1 bit is set for an MB configured
as Tx, the writing access done by CPU into the corresponding MB will be blocked.
When the FEN bit in the MCR is set (FIFO enabled), the function of the 8 least significant interrupt flags
(BUF7I - BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating
conditions of the FIFO, while BUF4I to BUF0I are not used.
Base + 0x0030
R
W
RESET:
0
BUF
31I
w1c
0
1
BUF
30I
w1c
0
2
BUF
29I
w1c
0
3
BUF
28I
w1c
0
4
BUF
27I
w1c
0
5
BUF
26I
w1c
0
6
BUF
25I
w1c
0
7
BUF
24I
w1c
0
8
BUF
23I
w1c
0
9
BUF
22I
w1c
0
10
BUF
21I
w1c
0
11
BUF
20I
w1c
0
12
BUF
19I
w1c
0
13
BUF
18I
w1c
0
14
BUF
17I
w1c
0
15
BUF
16I
w1c
0
R
W
RESET:
16
BUF
15I
w1c
0
17
BUF
14I
w1c
0
18
BUF
13I
w1c
0
19
BUF
12I
w1c
0
20
BUF
11I
w1c
0
21
BUF
10I
w1c
0
22
BUF
9I
w1c
0
23
BUF
8I
w1c
0
24
BUF
7I
w1c
0
25
BUF
6I
w1c
0
26
BUF
5I
w1c
0
27
BUF
4I
w1c
0
28
BUF
3I
w1c
0
29
BUF
2I
w1c
0
30
BUF
1I
w1c
0
31
BUF
0I
w1c
0
Figure 24-12. Interrupt Flags 1 Register (IFLAG1)
BUF31I–BUF8I — Buffer MB_i Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.
1 = The corresponding MB has successfully completed transmission or reception
0 = No such occurrence
BUF7I — Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag indicates
an overflow condition in the FIFO (frame lost because FIFO is full).
1 = MB7 completed transmission/reception or FIFO overflow
0 = No such occurrence
BUF6I — Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag indicates
that 5 out of 6 buffers of the FIFO are already occupied (FIFO almost full).
1 = MB6 completed transmission/reception or FIFO almost full
0 = No such occurrence
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
24-27