PXS20RM Datasheet, PDF (1332/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.5.2.15 Interrupt Filter Maximum Counter Register (IFMC0–IFMC31)
These registers are used to configure the filter counter associated with each digital glitch filter.
Address: Base + 0x1000–0x107C (32 registers)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
W
MAXCNTx
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 47-17. Interrupt Filter Maximum Counter Register (IFMC0–IFMC31)
Table 47-17. IFMC0_31 field descriptions
Field
MAXCNTx
Description
Maximum Interrupt Filter Counter setting.
Filter Period = T(CK)*3 (for 2 < MAXCNT < 6 )
Filter Period = T(CK)*MAXCNTx (for MAXCNT = 6,7,.... 15 )
For MAXCNT = 0, 1, 2 the filter behaves as ALL PASS filter.
MAXCNTx can be 0 to 15;
T(CK): Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value;
T(IRC): Basic Filter Clock Period: 62.5 ns (F = 16 MHz).
47.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler that is used to select the clock for all digital filter
counters in the SIUL.
47-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor