PXS20RM Datasheet, PDF (1288/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Semaphore Unit (SEMA4)
• When an attempted lock fails, the FSM enters a first state where it waits until the gate is unlocked.
• After it is unlocked, the FSM enters a second state where it generates an interrupt request to the
failed lock processor.
• When the failed lock processor succeeds in locking the gate, the IRQ is automatically negated and
the FSM returns to the idle state. However, if the other processor locks the gate again, the FSM
returns to the first state, negates the interrupt request, and waits for the gate to be unlocked again.
The notification interrupt request is implemented in a 3-bit, five-state machine, where two specific states
are encoded and program-visible as SEMA4_CP0NTF[GNn] and SEMA4_CP1NTF[GNn].
Offset: 0x0080 (SEMA4_CP0NTF)
0x0088 (SEMA4_CP1NTF)
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R _GN0
GN1
GN2
GN3
GN4
GN5
GN6
GN7
GN8
GN9
GN1
0
GN1
1
GN1
2
GN1
3
GN1
4
GN1
5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 43-4. Semaphores processor n IRQ notification (SEMA4_CP{0,1}NTF)
Table 43-4. SEMA4_CP{0,1}NTF field descriptions
Field
GNn
Description
Gate n Notification. This read-only field is a bitmap of the interrupt request notification from a failed
attempt to lock gate n.
0 No notification interrupt generated.
1 Notification interrupt generated.
43.3.4 Semaphores (secure) reset gate n (SEMA4_RSTGT)
Although the intent of the hardware gate implementation specifies a protocol where the locking processor
must unlock the gate, it is recognized that system operation may require a reset function to re-initialize the
state of any gate(s) without requiring a system-level reset.
To support this special gate reset requirement, the SEMA4 unit implements a secure reset mechanism
which allows a hardware gate (or all the gates) to be initialized by following a specific dual-write access
pattern. Using a technique similar to that required for the servicing of a software watchdog timer, the
secure gate reset requires two consecutive writes with predefined data patterns from the same processor to
force the clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTGT memory location. The most significant
byte (SEMA4_RSTGT[RSTGDP]) must be 0xE2; the least significant byte is a “don’t care” for this
reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTGT location. For this
write, the upper byte (SEMA4_RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the lower byte (SEMA4_RSTGT[RSTGTN]) specifies the gate(s) to be reset.
This gate field can specify a single gate be cleared or that all gates are cleared.
43-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor