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| PXS20RM Datasheet, PDF (512/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller | |||
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Fault Collection and Control Unit (FCCU)
Offset: 0x00Câ0x018 (4 registers)
Access: User read/write1
0
R CFC
W 31
Reset 0/12
1
CFC
30
0/12
2
CFC
29
0/12
3
CFC
28
0/12
4
CFC
27
0/12
5
CFC
26
0/12
6
CFC
25
0/12
7
CFC
24
0/12
8
CFC
23
0/12
9
CFC
22
0/12
10
CFC
21
0/12
11
CFC
20
0/12
12
CFC
19
0/12
13
CFC
18
0/12
14
CFC
17
0/12
15
CFC
16
0/12
16
17
18
19
20
21
R CFC CFC CFC CFC CFC CFC
W 15 14 13 12 11 10
Reset 0/12 0/12 0/12 0/12 0/12 0/12
1 Writable only in the CONFIG state
2 1 for FCCU_CF_CFG0; 0 otherwise
22
CFC
9
0/12
23
CFC
8
0/12
24
CFC
7
0/12
25
CFC
6
0/12
26
CFC
5
0/12
27
CFC
4
0/12
28
CFC
3
0/12
29
CFC
2
0/12
30
CFC
1
0/12
31
CFC
0
0/12
Figure 22-5. FCCU CF Configuration Register (FCCU_CF_CFG0..3)
Table 22-6. FCCU_CF_CFG0..3 field descriptions
Field
CFCx
Description
Critical fault configuration
0 Hardware recoverable fault.
1 Software recoverable fault.
The critical fault configuration defines the fault recovery mode.
Hardware-recoverable faults are self recovered (status flag clearing) if the root cause has been
removed.
SW recoverable faults are recovered (status flag clearing) by software clearing the related status
flag.
22.6.5 FCCU NCF Configuration Register (FCCU_NCF_CFG0..3)
The FCCU_NCF_CFGx register is accessible in write mode only in the CONFIG state. It contains the
configuration of each non-critical fault in terms of fault recovery management. The configuration depends
on the type of signaling of a fault event. HW recoverable faults should be configured only if a previous
latching stage captures and hold the physical fault otherwise the fault can be lost. All the other faults should
be configured as SW fault.
22-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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