PXS20RM Datasheet, PDF (236/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
• Port pin B[6] (see Figure 11-21). This signal is generated by using one of the 3-stage ripple counter
outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50%
duty cycle by the MC_CGM.
The MC_CGM also has an output clock enable register (see Section 11.3.1.1, Output Clock Enable
Register (CGM_OC_EN)) which contains the output clock enable/disable control bit.
11-22
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor