PXS20RM Datasheet, PDF (378/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

e200z4d Core Complex Overview
Figure 17-3 shows the user-mode special-purpose registers.
General Registers
Timers (Read only)
Condition Register
CR
Count Register
CTR SPR 9
Link
LR
SPR 8
XER
XER
SPR 1
General-Purpose Registers
GPR0
GPR1
•
•
•
GPR31
Accumulator
Time Base
TBL
TBU
SPR 268
SPR 269
Control Registers
SPR General (Read-only)
SPRG4 SPR 260
SPRG5 SPR 261
SPRG6 SPR 262
SPRG7 SPR 263
ACC
User SPR
USPRG0 SPR 256
Cache Register
(Read-only)
Cache Configuration
L1CFG0 SPR 515
L1CFG1 SPR 516
Category Registers
SPE Status and
Control Register
SPEFSCR SPR 512
Figure 17-3. e200z4d User Mode Programmer’s Model SPRs
The GPRs are accessed through instruction operands. Access to other registers can be explicit, by using
instructions for that purpose such as the Move to Special-Purpose Register (mtspr) and Move from
Special-Purpose Register (mfspr) instructions. Access to other registers can also be implicit, as part of the
execution of an instruction. Some registers are accessed both explicitly and implicitly.
17.3.1.1 Processor Version Register (PVR)
The PVR contains the processor version identification for the CPU core.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R1 0 0 0 0 0
TYPE
VERSION 0 0 0 0 MINREV MAJREV 0 0 0 1
W
Reset 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 17-4. Processor Version Register (PVR)
Table 17-1. PVR field descriptions
Field
TYPE
VERSION
MINREV
MAJREV
Processor type
010101 = e200z4d core
Processor version
0100 e200z4d core on this device
Minor revision number
Major revision number
Description
17-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor