PXS20RM Datasheet, PDF (678/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
25.3.4 PWM generator loading
25.3.4.1 Load enable
The LDOK bit enables loading of the following PWM generator parameters:
• The prescaler divisor—from the PRSC bits in the CTRL1 register
• The PWM period and pulse width—from the INIT and VALx registers
LDOK allows software to finish calculating all of these PWM parameters so they can be synchronously
updated. The PSRC, INIT, and VALx registers are loaded by software into a set of outer buffers. When
LDOK is set, these values are transferred to an inner set of registers at the beginning of the next PWM
reload cycle to be used by the PWM generator. These values can be transfered to the inner set of registers
immediately upon setting LDOK if LDMOD is set. Set LDOK by reading it when it is a logic zero and
then writing a logic one to it. After loading, LDOK is automatically cleared.
25.3.4.2 Load frequency
The LDFQ bits in the CTRL1 register select an integral loading frequency of one to 16 PWM reload
opportunities. The LDFQ bits take effect at every PWM reload opportunity, regardless the state of the
LDOK bit. The HALF and FULL bits in the CTRL1 register control reload timing. If FULL is set, a reload
opportunity occurs at the end of every PWM cycle when the count equals VAL1. If HALF is set, a reload
opportunity occurs at the half cycle when the count equals VAL0. If both HALF and FULL are set, a reload
opportunity occurs twice per PWM cycle when the count equals VAL1 and when it equals VAL0.
Counter
Reload
Change
Reload
Frequency
Every
two opportunities
to every
four opportunities
to every
opportunity
Figure 25-31. Full Cycle Reload Frequency Change
25-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor