PXS20RM Datasheet, PDF (1029/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Field
DTEn
Table 31-39. DMATXE field descriptions
Description
DMA Tx channel n enable
0 DMA Tx channel n disabled
1 DMA Tx channel n enabled
Note: When DMATXE = 0x0, the DMA Tx interface FSM is forced (soft reset) into the IDLE state.
31.10.25 DMA Rx enable register (DMARXE)
This register enables the DMA Rx interface.
Offset: 0x9C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R DRE DRE DRE DRE DRE DRE DRE DTE DRE DRE DRE DRE DRE DRE DRE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-42. DMA Rx enable register (DMARXE)
Table 31-40. DMARXE field descriptions
Field
DREn
DMA Rx channel n enable
0 DMA Rx channel n disabled
1 DMA Rx channel n enabled
Description
Note: When DMARXE = 0x0, the DMA Rx interface FSM is forced (soft reset) into the IDLE state.
31.11 DMA interface
The LINFlexD DMA interface offers a parametric and programmable solution with the following features:
• LIN Master node, TX mode: single DMA channel
• LIN Master node, RX mode: single DMA channel
• LIN Slave node, TX mode: 1 to N DMA channels where N = max number of ID filters
• LIN Slave node, RX mode: 1 to N DMA channels where N = max number of ID filters
• UART node, TX mode: single DMA channel
• UART node, RX mode: single DMA channel + timeout
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-53