PXS20RM Datasheet, PDF (56/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Introduction
• High immunity to EMI
• Short latency time due to an arbitration scheme for high-priority messages
• Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
• Receive features
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
• Programmable clock source
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.4.27 FlexRay
The FlexRay module provides the following features:
• Full implementation of FlexRay Protocol Specification 2.1 Rev. A
• 64 configurable message buffers can be handled
• Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
• Message buffers configurable as transmit or receive
• Message buffer size configurable
• Message filtering for all message buffers based on Frame ID, cycle count, and message ID
• Programmable acceptance filters for receive FIFO
• Message buffer header, status, and payload data stored in system memory (SRAM)
• Internal FlexRay memories have error detection and correction
1.4.28 Serial Communication Interface Module (UART)
The UART module with DMA support on this device features the following:
• UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor