PXS20RM Datasheet, PDF (464/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
0 = Timer channel is disabled.
20.4.5.2 DMA Request Select Registers (DREQ0, DREQ1)
eTimer_BASE ₀
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
+ $110
Read
Write
DRE 0 0 0 0 0 0 0 0 0 0
Q0_
EN
DREQ0[4:0]
Reset
0000 0 00000000000
Figure 20-22. DMA Request 0 Select Register (DREQ0)
eTimer_BASE ₀
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
+ $112
Read
Write
DRE 0 0 0 0 0 0 0 0 0 0
Q1_
EN
DREQ1[4:0]
Reset
0000 0 00000000000
Figure 20-23. DMA Request 1 Select Register (DREQ1)
DREQn_EN- DMA Request
Each of these fields enables DMA request outputs. Program the DREQ fields prior to setting the
corresponding enable bit. Clearing this enable bit will remove the request but won’t clear the flag that
is causing the request.
1 = DMA request enabled.
0 = DMA request disabled..
DREQn - DMA Request Select
Each of these two fields is used to select the source of one of the eTimer’s DMA requests. Enable a
DMA request in the channel specific INTDMA register and then use these registers to mux that request
onto the module level DMA request outputs.
Table 20-15. Values for DREQn
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
Selected DMA Request
Channel 0 CAPT1 DMA read request
Channel 0 CAPT2 DMA read request
Channel 0 CMPLD1 DMA write request
Channel 0 CMPLD2 DMA write request
Channel 1 CAPT1 DMA read request
Channel 1 CAPT2 DMA read request
Channel 1 CMPLD1 DMA write request
Channel 1 CMPLD2 DMA write request
Channel 2 CAPT1 DMA read request
Channel 2 CAPT2 DMA read request
20-22
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor