PXS20RM Datasheet, PDF (795/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.70 ECC Error Interrupt Flag and Enable Register (FR_EEIFER)
Base + 0x00F0
Write: Normal Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-101. ECC Error Interrupt Flag and Enable Register (FR_EEIFER)
This register provides the means to control the ECC related interrupt request lines and provides the
corresponding interrupt flags. The interrupt flags are cleared by writing 1, which resets the corresponding
report registers. For a detailed description see Section 26.6.24.2, Memory Error Reporting.
Table 26-80. FR_EEIFER Field Descriptions
Field
LRNE_OF
LRCE_OF
DRNE_OF
DRCE_OF
Description
Error Overflow Flags
LRAM Non-Corrected Error Overflow Flag — This flag is set to 1 when at least one of the
following events appears:
a) memory errors are detected but not corrected on CHI LRAM and interrupt flag LRNE_IF is
already 1.
b) memory errors are detected but not corrected on at least two banks of CHI LRAM
0 no such event
1 Non-Corrected Error overflow detected on CHI LRAM
LRAM Corrected Error Overflow Flag — This flag is set to 1 when at least one of the following
events appears:
a) memory errors are detected and corrected on CHI LRAM and interrupt flag LRCE_IF is already
1.
b) memory errors are detected and corrected on at least two banks of CHI LRAM
0 no such event
1 Corrected Error overflow detected on CHI LRAM
Note: Error Correction not implemented on CHI LRAM, flag will never be asserted.
DRAM Non-Corrected Error Overflow Flag — This flag is set to 1 when at least one of the
following events appears:
a) memory errors are detected but not corrected on PE DRAM and interrupt flag DRNE_IF is
already 1.
b) memory errors are detected but not corrected on at least two banks of the PE DRAM
0 no such event
1 Non-Corrected Error overflow detected on PE DRAM
DRAM Corrected Error Overflow Flag — This flag is set to 1 when at least one of the following
events appears:
a) memory errors are detected and corrected on PE DRAM and interrupt flag DRCE_IF is already
1.
b) memory errors are detected and corrected on at least two banks of PE DRAM
0 no such event
1 Corrected Error overflow detected on PE DRAM
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-83