PXS20RM Datasheet, PDF (1190/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Register Protection (REG_PROT)
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
X
X
X SLBRn[WE{3:0}]
update lock bits
SLB0 SLB1 SLB2 SLB3 SLBR[SLB{3:0}]
Figure 40-8. Change lock settings for 32-bit protected addresses
Figure 40-9 shows an example of mixed protection size configuration.
to SLB0 to SLB1 to SLB2 to SLB3 write data
1
X
X
1 SLBRn.WE[3:0]
update lock bits
SLB0 SLB1
0
SLB3 SLBR
Figure 40-9. Change lock settings for mixed protection
The data written to SLBRn[SLB{0}] is mirrored to SLBRn[SLB{1}] as the corresponding register is
16-bit protected. The data written to SLBRn[SLB{2}] is blocked as the corresponding register is
unprotected. The data written to SLBRn[SLB{3}] is written to SLBRn[SLB{3}].
40.4.2.2 Enable locking via mirror module space (area #3)
It is possible to enable locking for a register after writing to it. To do so, you must use the mirrored module
address space. Figure 40-10 shows one example.
16-Bit write to address 0x0008 ^{write to}
MR{9:8}
16-Bit write to address 0x2008 ^{write to}
MR{9:8}
no change
set lock bits
0 0 0 0 0 0 0 0 SLBR2
0 0 0 0 1 1 0 0 SLBR2
WE{3:0}
SLB{3:0}
WE{3:0} SLB{3:0}
Figure 40-10. Enable locking via mirror module space (area #3)
When writing to address 0x0008 the registers MR9 and MR8 in the protected module are updated. The
corresponding lock bits remain unchanged (left part of Figure 40-7).
40-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor