PXS20RM Datasheet, PDF (493/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
RAM causes the address, attributes and data associated with the access to be loaded into the PREAR,
PRESR, PREMR, PREAT, PREDRL, and PREDRH registers, and the appropriate flag (R1BC or RNCE)
in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no
RAM ECC event is defined to be handled for this module, accesses to this register will terminate with an
error.
See Figure 21-16 and Table 21-17 for the PREAR definition.
Register address: ECSM Base + 0x0060
0
1
2
3
4
5
R
W
RESET:
-
-
-
-
-
-
6
7
8
9
PREAR[0:15]
10 11 12 13 14 15
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PREAR[16:31]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Field
PREAR
= Unimplemented
Figure 21-16. Platform RAM ECC Address (PREAR) Register
Table 21-17. PREAR field descriptions
Description
Platform RAM ECC Address
This 32-bit field contains the faulting access address of the last, properly-enabled platform RAM
ECC event.
21.4.2.17 Platform RAM ECC Syndrome Register (PRESR)
The PRESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event
in the platform RAM. Depending on the state of the ECC Configuration Register, an ECC event in the
platform RAM causes the address, attributes and data associated with the access to be loaded into the
PREAR, PRESR, PREMR, PREAT, PREDRL, and PREDRH registers, and the appropriate flag (R1BC or
RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no
RAM ECC event is defined to be handled for this module, accesses to this register will terminate with an
error.
See Figure 21-17 and Table 21-18 for the PRESR definition.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-19