PXS20RM Datasheet, PDF (946/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

JTAG Controller (JTAGC)
Bit [0] — IDCODE Register ID
Bit [0] identifies this register as the device identification register and not the bypass register
29.3.1.4 TEST_CTRL register (cut2/3 only)
The TEST_CTRL register (supported on cut2/3 only) is a K-bit shift register path from TDI to TDO
selected when the ENABLE_TEST_CTRL instruction is active. The size (K) of the TEST_CTRL register
is defined by the TEST_CTRL_SIZE parameter. The TEST_CTRL register transfers its value to a parallel
hold register on the rising edge of TCK when the TAP controller state machine is in the Update-DR state.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R
W
1¹
0¹
1¹
1¹
1¹
0¹
1¹
0¹
0¹
0¹
0¹
Reset 0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
Figure 4. TEST_CTRL register (cut2/3 only)
NOTES:
1 _{This bit is reserved. The defined value will be used for future compatibility.}
Table 29-2. TEST_CTRL field descriptions
Field
PSTAT_SEL
TDO_SEL
RDY_SEL
RDY_ENABLE
Description
Processor Status Select
Selects whether the Core_0 or the Core_1 processor status outputs will appear on the
Nexus MDO pins when Processor Status Mode is enabled in the NPC Port Configuration
Register.
0 Core_0 PSTAT outputs selected.
1 Core_1 PSTST outputs selected.
TDO Select
Selects whether the Core_0 or Core_1 TDO output will be observable.
0 Core_0 TDO output selected.
1 Core_1 TDO output selected.
RDY Select
Selects whether the Nexus AUX interface RDY pad output buffer is fed by Core_0 or by Core_1
RDY_B signal
0 Core_0 provides RDY signal
1 Core_1 provides RDY signal
RDY Enable
Enables RDY functionality for corresponding GPIO pin. Setting this bit overrides SIUL output
muxing configuration for the corresponding pad.
0 Disables RDY functionality (Output mux for the pad is controlled by SIUL)
1 Enables RDY functionality (Output mux for the pad is controlled by JTAGC)
29.3.1.5 CENSOR_CTRL Register
The CENSOR_CTRL register is a 65-bit shift register path from TDI to TDO selected when the
ENABLE_CENSOR_CTRL instruction is active. The default reset value of the CENSOR_CTRL register
is 65’b0 . The CENSOR_CTRL register transfers its value to a parallel hold register on the rising edge of
29-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor