PXS20RM Datasheet, PDF (402/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Name
ECX
EMLM
CLM
HALT
HOE
ERCA
EDBG
Table 19-2. eDMA Control Register (DMACR) field descriptions
Description
Value
Error Cancel Transfer
0 Normal operation.
1 Cancel the remaining data transfer in the same
fashion as the CX cancel transfer. Stop the
executing channel and force the minor loop to be
finished. The cancel takes effect after the last write
of the current read/write sequence. The ECX bit
clears itself after the cancel cancel has been
honored. In addition to cancelling the transfer, the
ECX treats the cancel as an error condition; thus
updating the DMAES register and generating an
optional error interrupt (see Section 19.2.1.2, eDMA
Error Status (DMAES)).
Enable Minor Loop Mapping
0 Minor loop mapping disabled. TCDn.word2 is
defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set,
TCDn.word2 is redefined to include individual
enable fields, an offset field and the nbytes field. The
individual enable fields allow the minor loop offset to
be applied to the source address, the destination
address, or both. The nbytes field is reduced when
either offset is enabled.
Continuous Link Mode
0 A minor loop channel link made to itself will go
through channel arbitration before being activated
again.
1 A minor loop channel link made to itself will not go
through channel arbitration before being activated
again. Upon minor loop completion the channel will
active again if that channel has has a minor loop
channel link enabled and the link channel is itself.
This effectively applies the minor loop offsets and
restarts the next minor loop.
Halt eDMA Operations
0 Normal operation.
1 Stall the start of any new channels. Executing
channels are allowed to complete. Channel
execution will resume when the HALT bit is cleared.
Halt On Error
0 Normal operation.
1 Any error will cause the HALT bit to be set.
Subsequently, all service requests will be ignored
until the HALT bit is cleared.
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel
selection.
1 Round robin arbitration is used for channel
selection.
Enable Debug
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the
eDMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel
execution will resume when either the ipg_debug
input is negated or the EDBG bit is cleared.
19-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor