PXS20RM Datasheet, PDF (912/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
28.4.3 INTC Block Configuration Register (INTC_BCR)
INTC_BASE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 VTE 0 0 0 0 HVE
W
S_P
N_P
RC0
RC0
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 28-2. INTC Block Configuration Register (INTC_BCR)
The Block Configuration Register is used to configure options of the INTC.
VTES_PRC0 — Vector Table Entry Size
The VTES_PRC0 bit controls the number of ‘0’s to the right of
INTC_IACKR_PRC0[INTVEC_PRC0] in. If the contents of INTC_IACKR_PRC0 are used as an
address of an entry in a vector table, then the number of rightmost ‘0’s will determine the size of each
vector table entry. See Section 28.6.3, Code Compression’s Impact on Vector Table, for a use of the
VTES_PRC0 bit.
1 = 8 bytes
0 = 4 bytes
HVEN_PRC0 — Hardware Vector Enable
The HVEN bit controls whether the INTC is in hardware vector mode or software vector mode. Refer
to Section 28.2.1, Normal Mode, for the details of the handshaking with the processor in each mode.
1 = Hardware vector mode
0 = Software vector mode
28-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor