PXS20RM Datasheet, PDF (404/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
been modified by the eDMA engine and no longer represent the original parameters. When a transfer is
cancelled via the error cancel transfer mechanism (setting the DMACR[ECX]), the channel number is
loaded into the ERRCHN field and the ECX and VLD bits are set are set in the DMAES register. In
addition, an error interrupt may be generated if enabled. See Section 19.2.1.14, eDMA Error Low
(DMAERRL) Register, for error interrupt details.
The occurrence of any type of error causes the eDMA engine to immediately stop, and the appropriate
channel bit in the eDMA Error register to be asserted. At the same time, the details of the error condition
are loaded into the DMAES register. The major loop complete indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected.
See Figure 19-3 and Table 19-3 for the DMAES definition.
Register address: DMA_Offset + 0x0004
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R VLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECX
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18
R
0 CPE
W
RESET: 0 0 0
19 20 21 22
ERRCHN[0:5]
0000
23 24 25 26 27 28 29 30 31
SAE SOE DAE DOE NCE SGE SBE DBE
000000000
= Unimplemented
Figure 19-3. eDMA Error Status (DMAES) Register
Name
VLD
ECX
CPE
ERRCHN[0:5]
SAE
Table 19-3. eDMA Error Status (DMAES) field descriptions
Description
Logical OR of all DMAERRH and
DMAERRL status bits.
Transfer cancelled
Channel Priority Error
Error Channel Number or Cancelled
Channel Number
Source Address Error
Value
0 No DMAERR bits are set.
1 At least one DMAERR bit is set indicating a valid
error exists that has not been cleared.
0 No cancelled transfers.
1 The last recorded entry was a cancelled transfer via
the error cancel transfer input.
0 No channel priority error.
1 The last recorded error was a configuration error in
the channel priorities. All channel priorities are not
unique.
The channel number of the last recorded error
(excluding GPE and CPE errors) or last recorded
transfer that was error cancelled.
0 No source address configuration error.
1 The last recorded error was a configuration error
detected in the TCD.saddr field. TCD.saddr is
inconsistent with TCD.ssize.
19-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor