PXS20RM Datasheet, PDF (1027/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Field
SR
LIN Controller (LINFlexD)
Table 31-36. GCR field descriptions (continued)
Description
Soft reset
If the software writes a “1” to this field, the LINFlexD controller executes a soft reset in which the FSMs,
FIFO pointers, counters, timers, status registers, and error registers are reset but the configuration
registers are unaffected.
This field always reads “0”.
31.10.22 UART preset timeout register (UARTPTO)
This register contains the preset timeout value in UART mode, and is used to monitor the IDLE state of
the reception line. The timeout detection uses this register and the UARTCTO register described in
Section 31.10.23, UART current timeout register (UARTCTO).
Offset: 0x90
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
W
PTO
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Figure 31-39. UART preset timeout register (UARTPTO)
Field
PTO
Table 31-37. UARTPTO field descriptions
Description
Preset value of the timeout counter
Do not set PTO = 0 (otherwise, UARTSR[TO] would immediately be set).
31.10.23 UART current timeout register (UARTCTO)
This register contains the current timeout value in UART mode, and is used in conjunction with the
UARTPTO register (see Section 31.10.22, UART preset timeout register (UARTPTO)) to monitor the
IDLE state of the reception line. UART timeout works in both CPU and DMA modes.
The timeout counter:
• Starts at zero and counts upward
• Is clocked with the baud rate clock prescaled by a hard-wired scaling factor of 16
• Is automatically enabled when UARTCR[RXEN] = 1
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-51